The Builder
16–26 TOPS of real-world AI performance in under 3 watts. Built for Indian military drones. Zero foreign dependencies.
Every AI-enabled Indian military drone today runs on imported chips. One export ban, one sanction, one supply chain disruption — and India's drone fleet goes blind.
“India needs indigenous AI for defence and can’t rely on foreign models.”
of Indian military drones use foreign AI chips — NVIDIA Jetson, Hailo, or Google Coral. Total import dependency.
India has zero indigenous edge AI chip alternatives. No domestic supply chain exists for defense-grade AI inference hardware.
One export restriction and India's AI-enabled surveillance, reconnaissance, and autonomous drone operations are compromised.
DrishtiAI v2 combines INT4/INT8 dual precision with 2:4 structured sparsity to deliver effective throughput that matches chips on far more advanced process nodes.
| Parameter | Value |
|---|---|
| Architecture | 4-core NPU (16x16 systolic) + RISC-V RV32IM |
| Precision Modes | INT4 + INT8 dual mode (quantized from FP32) |
| Sparsity Support | 2:4 structured sparsity with hardware skip |
| Peak INT8 Compute | 2.048 TOPS @ 1GHz |
| Peak INT4 Compute | 8.192 TOPS @ 1GHz |
| Effective w/ Sparsity | 16-26 TOPS (mixed precision + 2:4) |
| Power Envelope | 1.5-3W (ASIC target) |
| On-chip SRAM | 2MB total (1.5MB unified + 4x128KB buffers) |
| Camera Interface | MIPI CSI-2, dual-lane, up to 1080p@30fps |
| Control CPU | RISC-V RV32IM (VexRiscv, open-source) |
| ASIC Process Node | 28nm (TSMC/Samsung) |
| Die Size Target | 5-10 mm2 |
| Cost at Volume | < $30 per chip |
| AI Workload | YOLOv8-nano/s detection + ByteTrack tracking |
Each NPU core contains a 16x16 systolic array of 256 processing elements, capable of INT8 or INT4 computation with hardware sparsity acceleration.
Matching global leaders in efficiency while being the only fully indigenous, defense-cleared option available to India.
| Feature | DrishtiAI v2 | Hailo-8 | Google Coral | NVIDIA Orin Nano |
|---|---|---|---|---|
| Origin | INDIA | Israel | USA | USA |
| Effective TOPS | 16-26 | 26 | 4.0 | 40 |
| Power | 1.5-3W | 2.5W | 2W | 7-15W |
| TOPS/Watt | 8-10 | 10.4 | 2.0 | 2.7-5.7 |
| INT4 Support | Yes | No | No | Yes |
| 2:4 Sparsity HW | Native | No | No | Yes |
| Defense Cleared | Indigenous | Import | Import | Import |
| Supply Chain | Sovereign | Foreign | Foreign | Foreign |
| Process Node | 28nm | 16nm | — | 8nm |
| Cost per Chip | < $30 | ~$50 | ~$60 | ~$200 |
A phased approach that de-risks every step — proving the design in simulation and FPGA before committing to ASIC tape-out.
Build and validate the core compute engine: 256 dual-precision PEs, INT4/INT8 modes, 2:4 sparsity engine, Python reference models, cycle-accurate simulation.
CompletedComplete NPU core with weight/activation buffers, hardware im2col, activation functions (ReLU/SiLU/GELU), and DMA engine. Run a full YOLO conv layer in simulation.
In ProgressPort to FPGA hardware. Integrate RISC-V core, AXI4 bus, and camera interface. Demonstrate live YOLOv8-nano inference at 15-25 FPS on real hardware.
UpcomingScale to multi-core operation. Implement pipeline mode across 4 NPU cores, add ByteTrack object tracking on RISC-V. Full detection + tracking demo.
UpcomingApply to India's Design Linked Incentive scheme with FPGA demo. ASIC synthesis targeting 28nm, physical design, and tape-out planning with DLI funding support.
UpcomingAligned with India Semiconductor Mission 2.0 and eligible for DLI scheme funding — up to 50% design cost reimbursement.
Design cost reimbursement up to Rs 15 crore under India's Design Linked Incentive scheme, plus 4-6% deployment incentives on net sales for 5 years.
Eligible for iDEX (Defence Innovation) funding and DRDO collaboration. Critical gap-filler for India's indigenous defense technology requirements.
Zero licensing costs. RISC-V open-source CPU core + open EDA toolchain. Full design IP owned by India. No ARM royalties, no vendor lock-in.
DrishtiAI is actively seeking strategic partners, defense collaborators, and investors aligned with India's semiconductor mission.
